Method and apparatus for generating a solid state circuit layout with in-design variability associated to the setting of analog signal processing parameters, and an integrated circuit design and an integrated circuit produced by applying such method

ABSTRACT

A Solid State Integrated Circuit Layout is generated by specifying an intended functionality assortment and translating the functionality assortment into various circuitry representations. The circuitry representations are converted into circuit items of an overall circuit, whilst configuring both first interfaces between interacting circuit items within the overall circuit and also second interfaces between further such circuit items and an external world in accordance with pre-determined interface specifications. In particular, for a situation wherein various such circuit items represent respective analog and/or steppable values to be specified on the basis of a circuit item in question, the parameter is assigned exclusively to a single such circuit item as a building block. The building block in question gets assigned a sufficient amount of in-design resizability and/or on-chip movability in accordance with a prespecified redefinability value range for the parameter in question.

BACKGROUND OF THE INVENTION

[0001] The invention relates to a method as recited in the preamble ofClaim 1. For designing a digital circuitry concept, such method has beendisclosed in U.S. Pat. No. 5,005,136. Broadly similar procedures may befollowed for designs that have a substantial amount of analog circuititems or parameters, such as relating to oscillators, filters,amplifiers, and other items. The present inventors have recognized thatmost present-day design approaches for analog circuitry will start froma rigid circuit specification as provided by an IC-manufacturer. Thelatter will generally optimize the design with respect to attaining asmall chip area and an optimized packing density. Such approach willresult however in a highly inflexible solution, that may need muchadditional time and effort for generating redesigns and amendments infunctionality or spec. Moreover, the design will in general feature onlylittle or no possibility for the reuse of building blocks, due to theabove focusing on area minimization. The above problem is especiallyrelevant in the initial phases of designing a mass-product, wheretime-to-market is extremely critical, and where frequent redesign cyclesare commonplace.

[0002] Now generally, the overall functional design will comprise amultiplicity of building blocks that are often arranged in a sequentialtype of organization for processing the signal or signals. Furthermore,the use of retrocoupling loops is a well-known feature. The variousbuilding blocks of such design may differ in layout view size among eachother by several orders of magnitude.

[0003] The problem so sketched is further aggravated in that thedesigning environment, especially in the initial phases thereof, oftenhas at least three players, to wit, the IC manufacturer, the set makerand the end user, who in principle should all benefit from an optimumdesign process. The present invention addresses in particular thedesigning for mass markets. This should lead to a product that will beaccepted immediately as regards its features, operativity, and price.Time-to-market should generally be minimum.

[0004] The above problem is extremely relevant for analog-orientedcircuit designs, inasmuch as for various parameters, such as voltage,frequency, etcetera, it is difficult to specify an exact optimum valuein advance, but only a more or less broad range of values may beindicated. This uncertainty would often apply to various differentparameters simultaneously, which renders the problem still more complex,and often quite unstable as regarding policy decisions. Furthermore, thedesign will often be bondpad-limited, in the sense that overall circuitsize is strongly dependent on the number and configuration of thebondpads, so that the merits of area minimization are limited only.

SUMMARY TO THE INVENTION

[0005] In consequence, amongst other things, it is an object of thepresent invention to allow that an optimization were effected in thedesign process that balances among the various categories of interestedparties, in that the ultimate fixing of the circuit may remainrelatively open until a late instant in the designing, or even stillafter ma d has become complete, where a particular variable remainsassociated to an individual building block, instead of being associatedto various building blocks simultaneously. Such multiple associatingwould in fact often necessitate a compromise between various, andsometimes conflicting, requirements.

[0006] Now therefore, according to one of its aspects the invention ischaracterized according to the characterizing part of Claim 1.

[0007] The phrase resizability space defines a key element of thecharacterizing part, meaning an amount of design area that is assignedto a single circuit item, wherein the intended range of value variationof an analog or steppable parameter assigned to that circuit item willcause an associated greater or lesser amount of use of the design areafor the building block resulting from the circuit item in question. Inparticular, for in the layout realizing an analog or steppable parametervalue, (1) the parameter in question is assigned to a single circuititem that is to be translated into a circuit block, and (2) the circuitblock in question gets enough space to allow amending the design fordifferent values of the parameter in question. In consequence, there aretwo mutually opposed directions of causality:

[0008] a. the top-down design that goes from overall functionality tospecific circuit blocks

[0009] b. the bottom-up assignment of the area that goes from themaximum area that is necessary for realizing the circuit block (orblocks) in question to the overall dimensions of the integrated circuit.

[0010] Essentially, an analog change or value step of a parameter willcause an associated change or step in the area necessary for theassociated circuit block. This differs essentially from the designing ofpotentiometers and the like, where the overall size of the circuit blockis always fixed, but the position of the tap can be amended. Anotherdifference of this presumably thick-film technology with the presentinvention is that a new round of the design would still need the samebig potentiometer, so that no further decrease in size would bepossible. Moreover, the principle of the present invention has a muchwider applicability, as demonstrated by the various preferredembodiments discussed herein. In particular, a prominent feature of manysuch embodiments is the occurrence of “empty” spaces that wereoriginally intended for a larger size of an associated circuit blockthan actually used for the embodiment in question. A particular aspectof the present invention is that the some circuit design quality (interms of optimum, i.e. minimum area) may be exchanged for fasterrealizing the circuit design proper. Of course, in the next designround, further optimization in view of overall circuit size would befeasible.

[0011] By itself, WO 95 32478 to IMP Inc. & Hans Klein, discusses anintegrated circuit with programmable analog functions & associatedprogramming techniques. The operation is typically described on p.4,1.25-29, where the configuration file is loaded on the chip toselectively activate the various programmable on-chip facilities. Inconsequence, there is no resizability space that may be used or not, butonly a maximum amount of space taken completely by the various actuallypresent circuit elements, that in fact are on a lower organizationallevel than the circuit blocks of the present invention. The differencewith the present invention is that we temporarily use more space toreach functionality, which space in a next design round may bediminished to get a less expensive solution. The reference is completelysilent in view of such subsequent usage of superfluous space to attain amore compact embodiment of the overall circuit.

[0012] The invention also relates to an apparatus arranged forimplementing a method as claimed in Claim 1, and to an integratedcircuit design and an integrated circuit realized through using theabove method. Generally, the designs in question will be less thanoptimum from a point of view of minimizing solid state area, but willinstead be flexible to a degree that hitherto was consideredunattainable for the high degree of VLSI complexity of those circuits.Further advantageous aspects of the invention are recited in dependentClaims.

BRIEF DESCRIPTION OF THE DRAWING

[0013] These and further aspects and advantages of the invention will bediscussed more in detail hereinafter with reference to the disclosure ofpreferred embodiments, and in particular with reference to the appendedFigures that show:

[0014]FIG. 1, a conceptual image of the interfacing between variousinterested parties, to wit IC-manufacture, Set-maker and End-user.

[0015]FIG. 2, a schematic of a single circuit item for use with thepresent invention;

[0016]FIG. 3, a schematic of a design of the invention having aplurality of building blocks;

[0017]FIG. 4, a first flow-chart of the design process;

[0018]FIG. 5, a second flow-chart of the design process;

[0019]FIG. 6, a third flow-chart of the design process;

[0020]FIG. 7, a conceptual image of the reuse of building blocks;

[0021]FIG. 8, a circuit layout generated according to the method of thepresent invention;

[0022]FIG. 9, an enlarged image of a part of FIG. 8;

[0023]FIG. 10, a conceptual arrangement of an apparatus for generating alayout as shown in FIG. 8;

[0024]FIG. 11, the global structure of a progammable building block;

[0025]FIG. 12, the global structure of ASiC with three levels ofinteraction.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0026]FIG. 1 shows a conceptual image of the multi-party interfacebetween an End-user, a Set-maker, and an IC-manufacturer. The innerregion 20 of the Figure illustrates the basic functionality of aparticular solid state circuit product that for simplicity will not bespecified further herein. The lens-shaped extremities A, B, C symbolizethe problems, requirements and associated solutions facing the variousinterested parties. An optimum design should meet the requirements asbest as possible. The situation may even be more complex, such as in thecase of an OEM being present.

[0027] Now, the customer or end-user (C) will experience the followingcategories of problems: the circuit is too expensive, its functionalityis not right, its performance insufficient, there are problems regardingfinal product size or weight, or there are inconveniences or expensesthrough incompatibility with usage in a multi-standard environment orwith standards that have geographical differences.

[0028] The set-maker (B) will experience the following categories ofproblems: the circuit is too expensive, its functionality is not right,its performance insufficient, there are problems regarding final productsize and/or weight, the design finalization is too late in view ofactions by a competitor, there are complex trade-offs to be made amongkey parameters, such as among performance, price, power consumption andsize, the product needs a costly manufacturing process throughtime-consuming alignments among circuit blocks, and there may be alogistic complexity through the necessity to provide special components.

[0029] The IC-manufacturer (A) will experience the following categoriesof problems: the product is too expensive, such as caused throughspecial components or alignment reprocessing, the functionality notright, inter alia through insufficient programmability, insufficientperformance, or over-due design finalization versus competitor'sactions, complex trade-offs must be made among key parameters, such asamong performance, price, power consumption and size, the productrequires a costly manufacturing process through time-consumingalignments among circuit blocks, and may cause logistic complexitythrough the necessity for providing special components. Generally, anoptimum product will be attained only through making various trade-offs.

[0030] In view of the above, the invention offers an Analog SiliconCompiler (ASiC) for fast and yet flexible prototyping of integratedcircuits. Quite often, designs produced by the invention will befirst-time right and will provide a high manufacturing yield through theuse or reuse of proven software components or Building Blocks (BB) thathave a high level of useful programmability. Such building blocks willoften be programmable in two qualitatively different ways to combinefist design with maximum flexibility. The hardware programmability ofthe building blocks will be used to meet the fundamental analog signalprocessing requirements. The software programmability of the buildingblocks will be used to increase manufacturing yield, to integratealignment points, and to adapt the functionality to the requirements ofthe end user.

[0031] A Top-Down Specification will give specification of UsefulProgrammability, in particular, specifying a General Structure of theASiC and a General Structure of BB's . The problems of theCustomer/End-User relate inter alia to personal taste and to a highlevel of customer satisfaction. The problems of the Set-Maker relate toFast Design-in and Inexpensive Production. The Problems of theIC-Manufacturer relate to Fast. & First-Time Right Design and HighManufacturing Yield.

[0032] ASiC Deliverables are Fast & Flexible Prototype IC's , thatprovide Added Value for Set-Maker and End-User. In order to find theright mix of specifications in terms of functionality, features, andcost price of the total product, the set-maker requires prototype IC'swith large flexibility. A similar example would be to introduceFlexibility/Personalization in the PC Industry by distinguishing a basicmodel and flexible add-on's like HDD, Memory, Display, and Mouse. Asecond example would be to introduce Flexibility/Personalization in thePersonal Digital Assistant Industry by enhancing programmability throughsoftware modulesASiC Deliverables provide fast and flexible prototypeIC's that give added value for both set-maker and end-User.Desirable/Useful Programmability relates to standards for use in amulti-standard environment, such as where AM inter-channel distancediffers between the US and Europe. Programmability ofuser-interface-orientation reacts to specific situations, such as byproviding gliding Stereo for FM receivers. Programmability of a newfeature that is not yet fully market tested allows early market exposurefor a set-maker, for attempting to raise customer satisfaction.

[0033] ASiC deliverables provide fast and flexible prototype IC's withadded value for the IC-manufacturer. In order to find the right mix ofspecifications, an IC-manufacturer requires prototype IC's with largeflexibility regarding basic functionality, features, supply voltage,supply current, chip size, number of bonding pads, encapsulation,required external components and other. Further aspects are:

[0034] Programmability of external control.

[0035] Automatic Alignment for high yield and fast design-in.

[0036] Programmability of new features which are not fully tested in themarket giving early market exposure for an IC-manufacturer to increasethe number of potential set-makers

[0037] Specification of a General Structure of Building Blocks

[0038] Analog Interfaces of BB's for signal processing within complexanalog architectures

[0039] Analog Interfaces of BB's for fixed or partly programmable(layout) parameter required for signal processing

[0040] Digital Interfaces of BB's (e.g. bus programmable) for AutomaticAlignment, Circumstantial Control, Fit to Personal Taste etc.

[0041] Standard Analog Interfaces of BB's

[0042] Information processing signals should preferably be balancedinstead of single-ended for better EMC performance

[0043] Maximum signal levels should be independent of Vcc, Temperature,manufacturing spread etc.

[0044] Control signals, such as AGC, AFC, PLL, should preferably bebalanced instead of single-ended for giving better EMC performance.

[0045] Universal DC-levels should provide for fast system design(click).

[0046] Specification of General Structure of BB's

[0047] DC Reference Voltage for Analog Interfaces of BB's should allowsignal processing within complex analog architectures.

[0048] DC Reference Voltage Current Sources should allow to controlpower consumption and impedance levels of BB's .

[0049] The description level of BB's can be at the following levels:

[0050] Mathematical Level

[0051] Behavioural Model usable in Standard Circuit Simulator

[0052] Circuit Model (Standard Circuit Simulator)

[0053] Layout Model, such including the added effects of parasiticcircuit elements

[0054] Fast & Efficient Transition from Prototype to Mass Productassociates to:

[0055] Circuit parameters, such as Vcc and dynamic range, and layoutparameters, such as fixed analog parameters like values of Resistors andCapacitors during prototype design.

[0056] Digital (Bus) parameter during evaluation of prototype atset-maker′ premises and final specification of the complete system

[0057] Fast Mass Product Specification associates to:

[0058] Fast transition from prototype, or the blueprint of the product,to a fully specified mass product with critical performance/price ratiowill be based on:

[0059] Fast trade-off among performance, such as Signal-to-Noise-Ratioand THD, versus cost price, such as determined by chip area, currentconsumption or supply voltage.

[0060] The most important trade-offs will be available as mathematicalmodels for each BB

[0061]FIG. 2 illustrates a schematic of a single circuit item for usewith the present invention. For brevity, the internal functionality 30of the item on an input signal 36 for therewith producing an outputsignal 38 has not been detailed. The circuit item is programmablethrough elements 32 and 34, through respectively associatedprogrammability interfaces 37, 39. The programmability may influencevarious analog or steppable parameters such as specified herebefore. Inparticular, the elements 32 and 34 may be programmable through hardwareor software. The programmability may be on the level of resizing thecircuit item, and may sometimes cause the moving of the circuit itemthrough the overall circuit layout. Another aspect is to introducediscrete elements that amend the operation, such as through amending thenumber of elements of a multi-element facility, such as the number ofsteps of a resistor ladder, or the number of stages of a multi-stagefilter to amend the filtering order which may influence the selectivityof the filter. For the latter, the adding or removing may be effected byhaving both a resistor bank and a capacitor bank. The amending may bedone by activating or deactivating a particular interconnection, or byshortcutting a particular element, respectively, as according to thevarious cases delineated in the foregoing. Another method is tointroduce mask programmability that may amend circuit properties untilat a late stage in manufacturing. A still further possibility foramending is through having programmable hardware, such as through theloading of a control register.

[0062]FIG. 3 illustrates an elementary schematic of a solid statecircuit (48) design according to the present invention featuring aplurality of circuit items (40, 42, 44, 46). Circuit item 46 isextendible in four steps as indicated by label 50 so that a particularanalog property thereof such as a capacitance value, may be variedaccordingly. Similar extendibility has been indicated with respect tocircuit items 42, 44. Circuit items 44 and 46 has been showninterconnected through lead 54 that terminates in interface elements 56,58, respectively. Circuit item 44 interfaces to an external worldthrough lead pair 52 that respectively terminate at bond pad pair 60.For brevity, the other elements depicted have not been labeled. Next toprogramming of the circuits through resizing as shown, also internalprogrammability through software may be provided, such as indicated inthe preceding paragraph. The amending of the value of a particularcircuit parameter, and the associated resizing of a layout block, may befollowed by moving the entire block in a convenient direction. If, forexample, the extension 50 of circuit block 46 were removed, the overallblock could be moved to the right, thereby shortening lead 54accordingly. This will however not influence the overall size of thelayout immediately. Such will quite often not even be very useful, ifthe layout size is bondpad-limited, so that the circumference lengthshould be kept fixed anyway.

[0063] In the design process, the amendable parameter value may bedescribed by an appropriate mathematical model. The actual setting of aparameter value may be effected through an interface to an external orinternal microprocessor item. The setting of a single operationalparameter value such as a frequency, may be effected through collectiveamending of two or more circuit size parameters, such as a resistanceand a capacitance combined. An advantageous aspect of the invention isthat parameter values may be kept independent of the design of abuilding block. The model produced by implementing the invention may beused straightaway for mag. Another instant of use of the invention is toprovide a simulation model of the intended circuit. The invention may beused for circuit design with a particular eye on higher level functions.In designing of a circuit, the sing point may be a mathematical modelthat has many parameters, which model allows to attain a technicallyoptimum result. Thereafter, the design goes stepwise to a behaviouralmodel that has fewer parameters, in that only part of the model ismathematical, whereas the remainder is circuitry already. Finally, themodel steps down to a transistor level, wherein the number of amendableparameters is generally still lower. For realizing the invention,various building blocks are parametrizable. Furthermore, in thestructure, the parameters are kept separately from each other. Thedesign starts with the conceptual defining of building blocks forherewith attaining the necessary functionality. Subsequently, thefunctionality is mapped on a plurality of building blocks as required.

[0064] Actual usage of the design methodology of the present inventionmay be effectively detected from various aspects of the design process,or from the using of the design for generating a particular circuitrylayout instance. In fact, the user interface towards the designer personwill often exhibit various key aspects of the invention, such as throughthe showing of menus, block representations, operationality curves, andmany others. As an elementary example, it would be possible to designand test a Phase Locked Loop and an Oscillator in many widely differentways. A first phase thereof could be to trade-off a dynamic range(Carrier-to-Noise Ratio CNR) versus circuit area and/or powerdissipation. It would be feasible to do so with a xls (EXCEL) programmodule constituting a part of the silicon compiler of the presentinvention. Thereafter, the system can be tested in various ways. For thePLL, such may be done on the Behavioural Model BM) level, such asthrough capture range, lock-range, the oscillator frequency, and otherparameters. This procedure will be followed from the Behavioural Modellevel down to the circuit level in a top-down design procedure.Thereafter, the test is started again on the BM level. All this would bevery time consuming with prior art technology. Next, the layout properwould produce certain parasitc values, that would need to be included inthe final test as well. Such approach that would combine the assessingof functional, economical (such as solid state area), multilevel (BM andcircuit aspects in alternation) and layout aspects (such as parasitecircuit elements), connectivity would represent an insurmountableproblem for all prior art approaches.

[0065]FIG. 4 illustrates a first flow-chart of the design processaccording to the present invention. The flow chart associates to arelatively lower level. In block 100, the designing process isinitiated. If necessary, a sufficient amount of hardware and softwarefacilities are assigned, such as being located on a server facility. Inblock 102, a set or assortment of functionality items is specified, suchas amplifiers, filters of various types, phase locked loops anddisccriminators, for therewith realizing the overall functionality ofthe circuitry to be designed. The circuitry may comprise analog as wellas digital functionality, but the present invention centers on effectingthe analog variable or steppable aspects of the above circuitry items ina favourable manner.

[0066] In block 104, the various items so specified are mapped onappropriate circuitry representations, that may be specifically providedby the designer, retrieved from a library facility, or decomposed intolower level items that collectively constitute a higher level item.Thereupon, these lower level representations will be mapped as well. Inblock 106, the various such representations are mapped on maximizedcircuit items. This may, as well as any of the various steps in theoverall designing process, be effected through a dialog with thedesigner or developer person, in a manner that by itself is commonplacein VLSI designing. In particular, such dialog may ask for the analogparameter values that would translate to a minimum allowable layout sizeof the final solid state circuit element, considering the electricalspecifications. In block 108, the interfaces, both between the variouscircuit items of block 106, and between the latter items and an outerworld as far as relevant, are specified. This would translate to linebundle widths, termination impedance values, configuring of amulti-circuit-element tree, specifying bondpads, and various othermechanisms that by themselves have become standard in VLSC designing.

[0067] In block 110, the various analog or steppable values are set.This may be effected immediately, such as through specifying a resistorvalue, or indirectly, such as through specifying a oscillator circuit'sfrequency. In a case where the latter depends on both a capacitor and aresistor value, appropriate values for those two may have to be selectedin a combined manner. Thereupon, the ultimate circuit now has arealization that allows the execution of a test. In block 112, such atest is executed, such as through simulation. In block 114 the test isevaluated in view of pre-specified target functionalities, such ascurrent consumption, stability, and others. The evaluation may have apositive result or otherwise. In the latter case, the process is routedbackwards to block 110 for further (re)-design or optimization. Ifpositive however, the process goes to the next level in block 116,wherein a certain implementation level is effected. This implementationmay be in one of various forms, such as in the form of a hardwareprototype, or rather as a simulation that will be subjected to inclusionin a next higher level of circuitry. The latter will eventually besubjected to its own appropriate test, which maps on one or more similarblocks as shown in FIG. 4, but on another level. If the test results ofthe simulated prototype have become available, they are forwarded to theother parties such as setmaker or IC manufacturer, discussed supra(block 118), who will then express their agreement or otherwise. Ifnegative (N), the process reverts to an earlier stage (110) foradjusting of appropriate analog or steppable values. If positive (Y), inblock 120 a pilot run is executed, which is again checked for customer'sor other parties' satisfaction. If negative (N), the analog values maybe adjusted again. If positive (Y), the next stage of the industrialcolumn is entered (124), for example, through implementing small scaleselling in the market. In general, there are repetitive possibilities tostep backwards in the process. Note that many of the tested aspectscould regard properties that are more or less a matter of choice,instead of having a good/faulty quality. Generally, the executing of aplurality of the above cycles in sequence will produce convergence.

[0068]FIG. 5 illustrates a second flow-chart of the design process, on asomewhat higher level than does FIG. 4. The process starts in block 126.In block 128, a prototype with hardware- and software options isproduced. In block 130 this is interfaced to the interested parties(FIG. 1). In block 132, the reactions are checked on satisfaction. Ifnegative (N), the process reverts to block 128. If positive (Y), theprocess proceeds to small-scale production (134). In block 136, themanufacturing yield is checked. If unsatisfactory (N), the processreverts to block 134, such as through amending one or more manufacturingparameters, or if considered necessary, even to block 128. Generally,the shorter step back will be preferred over the longer one, iffeasible. If satisfactory (Y), the design is reshaped to minimum chipsize, while retaining the dimensions considered necessary for for beingable to amend the circuit processing parameters. Next, in block 140, thecircuit is manufactured in mass production. In block 142, the result ischecked on its meeting of yield targets. If unsatisfactory (N), theprocess reverts to block 138, or, if considered necessary, to block 134,as considered supra. In rare cases, the reversion will extend as farback as to block 128. If the check is satisfactory however, the processproceeds to block 144, for continuing manufacture. In block 146, thedesigning process is considered terminated. Also here, eventually aconvergence will result.

[0069]FIG. 6 illustrates a third flow-chart of the design process, withparticular attention to the designing proper, i.e., up to block 128 inFIG. 5. In block 148, the process is started. In block 150, a circuitmodel is specified in an EXCEL module, expressing the relations of keyparameters thereof such as the most important signal processingparameters vs cost price based on chip area and bonding pads bymathematical expressions. In block 152, the model is checked for correctfunctionality. If unsatisfactory (N), the process reverts to block 150,for amending the circuit representation in question. If satisfactoryhowever (Y), the system proceeds to block 154, wherein the circuit isdecomposed into basic modules, such as have been consideredhereinbefore, and checked for correct mappability. If unsatisfactory(N), the process reverts to block 154, for amending the circuitrepresentation in question, such as by further decomposing of a buildingblock, or by designing a new building block that had yet been absentfrom an appropriate library therof.

[0070] If satisfactory however (Y), the system proceeds to block 158,wherein the overall circuit is composed from the basic modules, andchecked in block 160 once more on correct functioning, such as bysimulation. If unsatisfactory (N), the system reverts to block 158,wherein the circuit is amended, such as by setting a particularparameter to a new value. If satisfactory however (Y), the systemproceeds to block 162, wherein the circuit is translated into a layout,that in general will not be optimized for compactness, in that therelative positions of the various circuit elements have not beenoptimized, and will furthermore allow for setting of parameter values asdifferent from their provisional assignments. Then, in block 164, thelayout is checked for correctly operating. If unsatisfactory (N), thesystem reverts to block 162 for amending the layout. If satisfactoryhowever, the system proceeds to block 166, wherein the layout istranslated to include parasitic circuit components such as resistancesand capacitances, and checked for correct operation along the linesdiscussed earlier. If unsatisfactory (N), the system reverts to block166 for amending, such as for amending the parasite per se. Often, thesystem will even revert to block 162, or even (not shown) to a stillearlier block in the column, for amending the layout, or even thecircuit mapping to attempt in getting a better circuit performance. Ifsatisfactory however (Y), the system proceeds to output termination 170,and goes into the further process such as discussed with reference toFIG. 5.

[0071]FIG. 7 illustrates a conceptual image of the reuse of buildingblocks. Block 80 represents a first building block with originalfunction 82, and including two parameter variables associated to blocks84, 86, respectively, as determined by the area drawn in solid lines.Furthermore, block 90 represents the reuse of the above building block80, however, with different values of the above two parameter variables.This reuse translates into an exact replica of block 82 onto a copyblock 92, and accompanied by parameter value blocks 94, 96, drawn insolid lines. The latter respectively associate to blocks 84, 86. Asshown, block 94 is relatively shorter than block 84 in the horizontaldirection, but relatively higher in the vertical direction. On the otherhand, block 96 is relatively longer than block 86 in the horizontaldirection, and equal thereto in the vertical direction. For reason ofbetter comparison, the actual instance of the variable blocks has beendrawn in a solid line, whereas the “other” variable block has beensuperposed thereon in the form of an interrupted line. In practice, theprogrammability range of this hardware programming can be appreciable,such as various orders of magnitude. One instance is, for example, thata value is more or less proportional to the area covered, such as in thecase of a capacitor. The relationship may be more complex, such as for aresistor, where the parameter value may be proportional to the length,and inversely proportional to the width. The relation may be stepped,such as where adding of a stage to a filter bank will increase thefilter order by one.

[0072]FIG. 8 illustrates a circuit layout generated according to themethod of the present invention. The overall circuit represents ancomplete singe-hip audio tuner/pre-amplifier system for use with both AMand FM modulation. In the overall circuit, various building blocks havebeen delineated and highlighted. Furthermore, the four-edge-bondpadorganization has been clearly shown. Also, numerous empty spaces arevisible that could have allowed to physically extend an area allocatedto an implementation of a particular variable, or which space has notbeen used, to prevent inflexibility associated to over-close packing.Evidently, the overall packing is far from being close.

[0073] The various categories of building blocks, insofar as shown, arethe following. Item 202 is a resonance amplifier oscillator withvariable item 200 that determines the actual integration time thereof.Item 204 is a phase locked loop with item 206 determining the currentflow therein. Blocks 208, 209, 212 are three Automatic Gain Controlelements with blocks 210 (regarding 208, 212), and 216 (regarding 209)containing the respectively associated variable values for determiningthe integration time constants thereof Item 214 is a resonance amplifieroscillator. Item 220 is again a phase locked loop with an associatedcurrent parameter value item 218. Blocks 222 are three resonanceamplifiers. Item 224 is an automatic gain control with a variabledetermining item 226 for the time constant of the integration. Block 228is a digitally controlled varicap and block 230 a digital interface thatwill be discussed more in detail with reference to FIG. 9. The relevantoperational frequency of this subsystem is in the MHz region. Likewise,block 238 is a digitally controlled varicap and block 240 a digitalinterface. The relevant operational frequency of this further subsystemis in the 100 MHz region. Items 232 are againg two automatic gaincontrol blocks, with in blocks 236 the respectively associated timeconstant determining variable values. Block 234 is a low pass filtercontaining the associated threshold determining variable value. Block242 is is a resonance amplifier oscillator like block 214. Generally,the layout shows a clear distinction between irregular or “wild” logic,and regular structures such as those that define a resistor or acapacitance.

[0074] In the above, the resonance amplifier and resonance amplifieroscillators have reusable blocks as discussed with reference to FIG. 7,supra, which may be executed for example with hardwired resistance andcapacitance parameter values. On the other hand, the combination of adigital interface and a digitally controlled varicap, also in FIG. 8,effectively constitute a capacitance with a value that may be setaccording to the present invention. The two sub-blocks in questioninterface to each other on plural bit lines, of which the exact numbercontrols the capacitance. value. In fact, this number is softwareprogrammable for setting the associated parameter value. It should beunderstood from the foregoing that a resonance amplifier may have itsfrequency chosen in two different manners: either on the basis of thehardware extension or size of one or more particular circuit elements,or, otherwise, as based on software digital programming of a digitalnumber that governs the actual operativity of the circuit element inquestion. Depending on the instant when the value should be amended, andon various other aspects or circumstances, one or the other of the twoqualitatively filly distinct approaches method would present the mostpreferable solution. The programmability can be inherent in thedefinitions of the various building blocks.

[0075] In general, the building blocks generally have repetitivestructures for facilitating a straight-forward design. Now, theparticular setup of the circuit of FIG. 8 for realizing thefunctionality as indicated supra may be realized by persons skilled inthe art in a straightforward manner, as constituted from the variousbuilding blocks delineated supra. Furthermore, given the layoutaccording to the Figure, that in fact has plenty of detail on a muchsmaller scale than can be shown in this overall image, the translatingto an actual hardware realization is straightforward to a person skilledin the art of semiconductor processing.

[0076] Now, the above discussion of various building blocks has givenvariables assigned to these respective building blocks. Furthermore, itshould be clear from the layout that various blocks have furtherrepetitive inside structures. Certain ones thereof may be fixed to thebuilding block in question. In other situations, a particular buildingblock may contain a subaltern or hierarchically lower building blockthat itself contains one or more variables assigned thereto and withassociated parameter value(s) settable in the same manner as discussedfor the higher level variables hereinbefore. For brevity however, afuller discussion thereof has been left out.

[0077]FIG. 9 illustrates an enlarged image of a part of FIG. 8, and inparticular, the combination of a digitally controlled interface and adigitally controlled varicap. The Figure effectively blows up items 228and 230 in FIG. 8. Item 250 at left represents an 11 bit capacitor bank,that in consequence will have a spread from 1 to 2¹¹. Item 252 is aserial to parallel converter, of which the 11 parallel bits control thecapacitor bank that interfaces to the remainder of the circuit.Likewise, item 254 is a register bank for storing the 11 control bitsfor the capacitor bank control. Finally, item 256 represents twoDigital-to-Analog Convertors DAC. Taken as a whole, the circuit operatesas a programmable capacitor.

[0078]FIG. 10 illustrates a conceptual arrangement of an apparatus forgenerating a layout as shown in FIGS. 8, 9. At left, the generating ofthe conceptual aspects of the circuit are symbolized. Memories 260, 262store mathematical expressions and their translation to circuitrepresentations, respectively, so that the selecting thereof on userinterface 266 will produce circuit representations on a rather abstractbasis on user output device 268 that may contain a printer and the likenext to the visual display shown. On the other side, memory 270 containsscalable layouts of various circuit elements and parasitic accessoriesto such such circuit elements, and memory 274 contains simulationprograms for checking on the actual behaviour of a conceived circuit orsubcircuit item. Processor 272 will run the simulation of the circuitrealized in layout either with or without the parasites discussedearlier and check the operation for compliance with user-enteredrequirements on interface 266 that may contain other elements than thekeyboard shown symbolically. Central processor 264 controls the userinterface and the various other subsystems, and allows to construct thecircuit representations (item 104 in FIG. 4).

[0079]FIG. 11 illustrates the global structure of a progammable buildingblock on an abstract level. The left hand column lists the various partsof such building block, the right hand column lists the respectivelyassociated important aspects of those parts. Now first, there is the“active circuit” or “core” of the building block in question. This coredefines the overall functionality and the limits to this functionality,especially in terms of RF performance and noise. Changing of themanufacturing technology could cause great changes in those performancelimits, such as the changing from MOS to bipolar or vice versa Thisfirst stage generally will require much design effort. Next, at leftthere are passive parameters (R, C, L) that will be fixed in theultimate design. Inasmuch as realizing these parameters may requirevarious on chip elements, they may under certain circumstances requirerelatively much chip area. These parameters are programmable only in thelayout, and will generally be little sensitive to changes of thetechnology. However, the selection of the analog or steppable valuesmust be done relatively early in the design process. Finally, at leftthere are passive programmable parameters. Also here the largest sizefor effecting the parameter value must be available on the chip, but theparameters are programmable via a BUS or another transfer mechanism thatcommunicates control information. This procedure will allow to delay thefixating operation until a very late stage of the manufacturing process.The effecting of the parameter values is an important determinant of thecircuit's price.

[0080]FIG. 12 illustrates the global structure of ASiC with three highlyinteracting levels. The top level is the relational level, of whichcharacteristic aspects are a library of relations between performance invarious aspects, and cost price. Moreover, there are rules forgenerating new relations. These rules determine the interaction with thebuilding block level to be discussed next. On a first level ofinteraction, the rules may be expressed by explicit qualitative orquantitative relations. Another possibility for expressing these rulesis through generating various instances or quantitative examples of thecircuit. The determination of the ultimate performance and price datamay then be done by interpolation, extrapolation, or by nomography-liketechniques that by themselves have been in widespread use in variousbranches of technology. For brevity, no further discussion thereon isgiven here.

[0081] The performance and cost price are used on the right of theFigure to get support in Vendor-Buyer relations, to position an emergingproduct, and in later stages, to optimize a mature product. The lattermay be done in various ways. A first one is eliminate invisibleperformance of the circuit. For example, in a chain of circuitfunctions, the overall performance is often determined by a “weaker”function. Such situation will often be the result when usingpre-existing designs for those “stronger” circuit functions.Repositioning of those other circuit functions to lower performance,such as a lower S/N ratio, may then lead to a lower overall price, butunchanged performance. Another type of optimization is the improving ofcertain circuit functions, such as the lowering of power consumption, orthe effective diminishing of noise.

[0082] The next lower Circuit level of the Figure concerns the buildingblocks (BB). At left, characteristic aspects thereof are a library of BBcircuits, and furthermore rules for defining new BB's . At right, theapplication of these building blocks is to support the generating ofprogrammable designs, and furthermore, providing the sheer possibilityto attain first-time-right designs. The interactions with the next lowerlevel in the Figure have been indicated at left, inasmuch as theseinteractions imply parasitic elements, and the various active circuitelements and associated parameters.

[0083] The lowest level in the Figure is the layout level. At left,characteristic aspects are a library of programmable layouts of BuildingBlocks, and rules for the defining of new programmable layouts. Theapplication thereof at the right is to support flexible layout withrespect to the encapsulation of the final circuit, and to ensure asufficient degree of testability.

[0084] Through applying the present invention, it has been foundpossible to use or reuse programmable circuit elements in designingvarious electronic analog circuit designs that are first-time-right. Ithas also been found possible to execute redesigns and/or design changesin an extremely fast and transparent maimer, whilst always being able toquasi-instantaneously present both operating parameters and price,either through analytic-relationship tools, or through anomographic-like approach.

[0085] Now the invention has been fully described with reference to thepreferred embodiments. However, persons skilled in the art willrecognize various changes and amendments thereto. As long as these wouldnot depart from the scope of the invention as claimed in theaccompanying Claims, they should in consequence being construed asforming part of the invention.

1. A method for generating a Solid State Integrated Circuit Layout byspecifying an intended functionality assortment, translating saidfunctionality assortment into various circuitry representations,converting said circuitry representations into circuit items of anoverall circuit, whilst configuring both first interfaces betweeninteracting circuit items within said overall circuit and also secondinterfaces between further such circuit items and an external world inaccordance with predetermined interface specifications, said methodbeing characterized in that, for a situation wherein various suchcircuit items represent respective analog and/or steppable values of aparameter to be specified on the basis of a circuit item in question,the parameter is assigned exclusively to a single such circuit item tobe realized as a building block, and the building block in question getsassigned a sufficient amount of in-design resizability space inaccordance with a prespecified redefinability value range for theparameter in question.
 2. A method as claimed in claim 1, wherein saiddesign is effected in a plurality of cycles, and wherein convergence isattained through in successive such cycles amending a size of one ormore particular circuit items within a respectively assigned in-designspace for so attaining the desired functionality assortment.
 3. A methodas claimed in claim 1, wherein such building block gets in itsdefinition assigned a hardware and/or software programmability interfacewith respect to an applicable value range for the parameter beingassigned to the building block in question.
 4. A method as claimed inclaim 1, wherein at least one such building block has assigned theretoat least two parameter values.
 5. A method as claimed in claim 1,wherein at least two such parameter values are programmable inrespectively associated building blocks that with respect to each otherare configured into a hierarchical structure.
 6. A method as claimed inclaim 1, wherein a particular building block that represents acombination of a functionality circuit item and one or more parametersis reused in such design in two or more versions as being associated torespective such circuit item instances and, as the case may be, torespectively different parameter values.
 7. An apparatus being arrangedfor implementing a method as claimed in claim 1 for generating a SolidState Integrated Circuit Layout and having receive means for receivingan intended functionality assortment as specified, translating means fortranslating said functionality assortment into various circuitryrepresentations, converting means for converting said circuitryrepresentations into circuit items of an overall circuit and includingconfiguring means for configuring both first interfaces betweeninteracting circuit items within said overall circuit and also secondinterfaces between further such circuit items and an external world inaccordance with predetermined interface specifications, said apparatusbeing characterized by having assign means for, in a situation whereinvarious such circuit items represent respective analog and/or steppablevalues of a parameter to be specified on the basis of a circuit item inquestion, assigning the parameter exclusively to a single such circuititem to be realized as a building block, and assigning to the buildingblock in question a sufficient amount of in-design resizability space inaccordance with a prespecified redefinability value range for theparameter in question.
 8. An apparatus as claimed in claim 7, whereinthe assign means is arranged for assigning to such building block in itsdefinition a hardware and/or software programmability interface withrespect to an applicable value range for the parameter being assigned tothe building block in question.
 9. A Solid State Integrated Circuitdesign, having been implemented through using a method as claimed inclaim 1, on the basis on specifying an intended functionalityassortment, translating said functionality assortment into variouscircuitry representations, converting said circuitry representationsinto circuit items of an overall circuit, whilst configuring both firstinterfaces between interfacing circuit items within said overall circuitand also second interfaces between further such circuit items and anexternal world in accordance with predetermined interfacespecifications, said circuit design being charactized in that, for asituation wherein various such circuit items represent respective analogand/or steppable values of a parameter to be specified on the basis of acircuit item in question, the parameter has been assigned exclusively toa single such circuit item to be realized as a building block, and thebuilding block in question has gotten assigned a sufficient amount ofin-design resizability space in accordance with a prespecifiedredefinability value range for the parameter in question.
 10. Anintegrated circuit design as claimed in claim 9, provided with a circuititem which as a building block is programmable in at least twoqualitatively different ways to combine faster design with flexibility.11. An integrated circuit design as claimed in Claim B, provided withhardware programmability of the building blocks for use to meet one ormore fundamental analog signal processing requirements.
 12. Anintegrated circuit design as claimed in claim 9, provided with softwareprogrammability of the building blocks for use in one or more of thefollowing aspects: to increase manufacturing yield, to integratealignment points, and to adapt the functionality to a requirement of anend user.
 13. An integrated circuit having been designed through using amethod as claimed in claim 1, on the basis on specifying an intendedfunctionality assortment, translating said functionality assortment intovarious circuitry representations, converting said circuitryrepresentations into circuit items of an overall circuit, whilstconfiguring both fast interfaces between interacting circuit itemswithin said overall circuit and also second interfaces between furthersuch circuit items and an external world in accordance withpredetermined interface specifications, said circuit being characterizedin that, for a situation wherein various such circuit items representrespective analog and/or steppable values of a parameter to be specifiedon the basis of a circuit item in question, the parameter has beenassigned exclusively to a single such circuit item to be realized as abuilding block, and the building block in question has gotten assigned asufficient amount of in-design resizability space in accordance with aprespecified redefinability value range for the parameter in question.14. An integrated circuit as claimed in claim 13, and having analogand/or digital programming facilities for programming at least one ofsaid parameter values after manufacturing.
 15. A method for generating aSolid State Integrated Circuit Layout by specifying an intendedfunctionality assortment, translating said functionality assortment intovarious circuitry representations, converting said circuitryrepresentations into circuit items of an overall circuit, whilstconfiguring both first interfaces between interacting circuit itemswithin said overall circuit and also second interfaces between furthersuch circuit items and an external world in accordance withpredetermined interface specifications according to claim 1, said methodbeing characterized by executing said generating in a top-down designflow, wherein the following design levels are executed: a. specifying anoverall circuit functionality and key parameter trade-offs, b. detailingsaid overall circuit functionality into multiple library layout buildingblocks, c. (re)-assigning to said library blocks various reprogammableparameter values, d. testing the overall circuit versus targetperformance, and if necessary, returning to c.), e. introducingparasitic values associated to the overall circuit as specified, f.testing the parasited circuit versus target performance, and ifnecessary, returning to c.).
 16. A method as claimed in claim 15,wherein said specifying is effected in an EXCEL program module.
 17. Amethod as claimed in claim 15, wherein at least one building block has asoft-ware programmable multi-value range for an associated furtherparameter value.